Pillar bump with barrier layer

ABSTRACT

A copper pillar bump has a surface covered with by a barrier layer formed of a copper-containing material layer including a group III element, a group IV element, a group V element or combinations thereof. The barrier layer depresses the copper diffusion and reaction with solder to reduce the thickness of intermetallic compound between the pillar pump and solder.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority of U.S. Provisional PatentApplication Ser. No. 61/258,393, filed on Nov. 5, 2009, which isincorporated herein by reference in its entirety.

TECHNICAL FIELD

This disclosure relates to the fabrication of integrated circuitdevices, and more particularly, to the fabrication of bump structures inintegrated circuit devices.

BACKGROUND

Modern integrated circuits are made up of literally millions of activedevices such as transistors and capacitors. These devices are initiallyisolated from each other, but are later interconnected together to formfunctional circuits. Typical interconnect structures include lateralinterconnections, such as metal lines (wirings), and verticalinterconnections, such as vias and contacts. Interconnections areincreasingly determining the limits of performance and the density ofmodern integrated circuits. On top of the interconnect structures, bondpads are formed and exposed on the surface of the respective chip.Electrical connections are made through bond pads to connect the chip toa package substrate or another die. Bond pads can be used for wirebonding or flip-chip bonding.

Flip-chip packaging utilizes bumps to establish electrical contactbetween a chip's I/O pads and the substrate or lead frame of thepackage. Structurally, a bump actually contains the bump itself and aso-called under bump metallurgy (UBM) located between the bump and anI/O pad. An UBM generally contains an adhesion layer, a barrier layerand a wetting layer, arranged in this order on the I/O pad. The bumpsthemselves, based on the material used, are classified as solder bumps,gold bumps, copper pillar bumps and bumps with mixed metals. Recently,copper pillar bump technology is proposed. Instead of using solder bump,the electronic component is connected to a substrate by means of copperpillar bump, which achieves finer pitch with minimum probability of bumpbridging, reduces the capacitance load for the circuits and allows theelectronic component to perform at higher frequencies.

The Cu pillar bump flip-chip assembly has the following advantages: (1)better thermal/electric performance, (2) higher current carryingcapacity, (3) better resistance to electromigration, thus longer bumplife, (4) minimizing molding voids—more consistence gaps between Cupillar bumps. Also, a lower cost substrate is possible by usingCu-pillar controlled solder spreading, eliminating lead-free teardropdesign. However, there are concerns regarding the Intermetallic Compound(IMC) generated between the Cu pillar bump and the solder duringannealing. When used with Sn solder material, sufficient Cu diffusionfrom Cu pillar bump into the solder forms thick IMC such as Cu₆Sn₅ andCu₃Sn through the reaction between the diffused Cu and Sn in the solder.Thick IMC layers reduce mechanical strength of the Cu pillar bumpbecause the IMC layers are brittle. The IMC becomes scallops and spallsoff the interface. With thicker Sn solder, longer annealing process andabundant Cu source make Cu₃Sn thicker, and also the size of Cu₆Sn₅becomes large. Total transfer of the ductile solder to harder IMC lowersthe shear strength of the structure. The IMC formation will cause bumpcrack or unwanted stress, the thicker IMC also results in poor adhesion.

BRIEF DESCRIPTION OF THE DRAWINGS

The objects, features and advantages of this disclosure will becomeapparent by referring to the following detailed description of exemplaryembodiments with reference to the accompanying drawings, wherein:

FIG. 1 to FIG. 4 are cross-sectional diagram depicting an exemplaryembodiment of a Cu pillar bump process;

FIG. 5 is a cross-sectional diagram depicting an exemplary embodiment ofa Cu pillar bump; and

FIG. 6 is a cross-sectional diagram depicting an exemplary embodiment ofa flip-chip assembly; and

FIG. 7 is a cross-sectional diagram depicting an exemplary embodiment ofa flip-chip assembly.

DETAILED DESCRIPTION

In the following description, numerous specific details are set forth toprovide a thorough understanding of the disclosure. However, one havingan ordinary skill in the art will recognize that the disclosure can bepracticed without these specific details. In some instances, well-knownstructures and processes have not been described in detail to avoidunnecessarily obscuring the disclosure.

Reference throughout this specification to “one embodiment” or “anembodiment” means that a particular feature, structure, orcharacteristic described in connection with the embodiment is includedin at least one embodiment. Thus, the appearances of the phrases “in oneembodiment” or “in an embodiment” in various places throughout thisspecification are not necessarily all referring to the same embodiment.Furthermore, the particular features, structures, or characteristics maybe combined in any suitable manner in one or more embodiments. It shouldbe appreciated that the following figures are not drawn to scale;rather, these figures are merely intended for illustration.

Herein, cross-sectional diagrams of FIG. 1 to FIG. 4 illustrate anexemplary embodiment of a Cu pillar bump process. At the outset, it isassumed that a pillar or bump is provided comprising copper. This pillaror bump may be applied directly on an electrical pad on a semiconductorchip for a flip chip assembly or other similar application.

In FIG. 1, an example of a substrate 10 used for bump fabrication maycomprise a semiconductor substrate as employed in a semiconductorintegrated circuit fabrication, and integrated circuits may be formedtherein and/or thereupon. The semiconductor substrate is defined to meanany construction comprising semiconductor materials, including, but isnot limited to, bulk silicon, a semiconductor wafer, asilicon-on-insulator (SOI) substrate, or a silicon germanium substrate.Other semiconductor materials including group III, group IV, and group Velements may also be used. The substrate 10 may further comprise aplurality of isolation features (not shown), such as shallow trenchisolation (STI) features or local oxidation of silicon (LOCOS) features.The isolation features may define and isolate the variousmicroelectronic elements (not shown). Examples of the variousmicroelectronic elements that may be formed in the substrate 10 includetransistors (e.g., metal oxide semiconductor field effect transistors(MOSFET), complementary metal oxide semiconductor (CMOS) transistors,bipolar junction transistors (BJT), high voltage transistors, highfrequency transistors, p-channel and/or n-channel field effecttransistors (PFETs/NFETs), etc.); resistors; diodes; capacitors;inductors; fuses; and other suitable elements. Various processes areperformed to form the various microelectronic elements includingdeposition, etching, implantation, photolithography, annealing, andother suitable processes. The microelectronic elements areinterconnected to form the integrated circuit device, such as a logicdevice, memory device (e.g., SRAM), RF device, input/output (I/O)device, system-on-chip (SoC) device, combinations thereof, and othersuitable types of devices.

The substrate 10 further includes inter-layer dielectric layers and ametallization structure overlying the integrated circuits. Theinter-layer dielectric layers in the metallization structure includelow-k dielectric materials, un-doped silicate glass (USG), siliconnitride, silicon oxynitride, or other commonly used materials. Thedielectric constants (k value) of the low-k dielectric materials may beless than about 3.9, or less than about 2.8. Metal lines in themetallization structure may be formed of copper or copper alloys. Oneskilled in the art will realize the formation details of themetallization layers. A contact region 12 is a top metallization layerformed in a top-level inter-layer dielectric layer, which is a portionof conductive routs and has an exposed surface treated by aplanarization process, such as chemical mechanical polishing (CMP), ifnecessary. Suitable materials for the conductive region 12 may include,but are not limited to, for example copper (Cu), aluminum (Al), AlCu,copper alloy, or other mobile conductive materials. In one embodiment,the contact region 12 is a metal pad region 12, which may be used in thebonding process to connect the integrated circuits in the respectivechip to external features.

FIG. 1 also illustrates a passivation layer 14 formed on the substrate10 and patterned to form an opening 15 exposing a portion of theconductive region 12 for allowing subsequent post passivationinterconnect processes. In one embodiment, the passivation layer 14 isformed of a non-organic material selected from un-doped silicate glass(USG), silicon nitride, silicon oxynitride, silicon oxide, andcombinations thereof. In another embodiment, the passivation layer 14 isformed of a polymer layer, such as an epoxy, polyimide, benzocyclobutene(BCB), polybenzoxazole (PBO), and the like, although other relativelysoft, often organic, dielectric materials can also be used.

A post passivation interconnect (PPI) process is then performed on thepassivation layer 14. Referring to FIG. 1, layers 16 including anadhesion layer and a seed layer are formed on the passivation layer 14to line the sidewalls and bottom of the opening 15. The adhesion layer,also referred to as a glue layer, is blanket formed, covering thepassivation layer 14 and the sidewalls and the bottom of opening 15. Theadhesion layer may include commonly used barrier materials such astitanium, titanium nitride, tantalum, tantalum nitride, and combinationsthereof, and can be formed using physical vapor deposition, sputtering,and the like. The adhesion layer helps to improve the adhesion of thesubsequently formed copper lines onto passivation layer 14. The seedlayer is blanket formed on the adhesion layer. The materials of the seedlayer include copper or copper alloys, and metals such as silver, gold,aluminum, and combinations thereof may also be included. The seed layermay also include aluminum or aluminum alloys. In an embodiment, the seedlayer is formed of sputtering. In other embodiments, other commonly usedmethods such as physical vapor deposition or electroless plating may beused. For clarity, the seed layer and the adhesion layer are shown aslayers 16 in the drawings.

Also, a post passivation interconnect (PPI) line 18 is formed on thelayers 16 to fill the opening 15. Using a mask and a photolithographyprocess, a conductive material fills the opening 15 of the passivationlayer 14 and the opening of the mask followed by removing the mask andthe exposed layers 16. The conductive material formed on the layers 16and filling the opening 15 serves as the PPI line 18. The PPI line 18may include, but is not limited to, for example copper, aluminum, copperalloy, or other mobile conductive materials. The PPI line 18 may furtherinclude a nickel-containing layer (not shown) on the top acopper-containing layer. The PPI formation methods include plating,electroless plating, sputtering, chemical vapor deposition methods, andthe like. The PPI line 18 connects the contact region 12 to bumpfeatures. The PPI line 18 may also function as power lines,re-distribution lines (RDL), inductors, capacitors or any passivecomponents. The PPI line 18 may have a thickness less than about 30 μm,for example between about 2 μm and about 25 μm. Then the exposedportions of the layers 16 including the adhesion layer and the seedlayer are removed. The removal step may include a wet etching process ora dry etching process. In one embodiment, the removal step includes anisotropic wet etching using an ammonia-based acid, which may be a flashetching with a short duration.

Next, a dielectric layer 20, also referred to as an isolation layer or apassivation layer, is formed on the exposed passivation layer 14 and thePPI line 18. The dielectric layer 20 may be formed of dielectricmaterials such as silicon nitride, silicon carbide, silicon oxynitrideor other applicable materials. The formation methods include plasmaenhance chemical vapor deposition (PECVD) or other commonly used CVDmethods. A polymer layer 22 is formed on the dielectric layer 16 throughthe steps of coating, curing, descum and the like. Lithographytechnology and etching processes such as a dry etch and/or a wet etchprocess are then performed to pattern the polymer layer 22, thus anopening 23 is formed to pass through the polymer layer 22 and expose aportion of the PPI line 18 for allowing subsequent bump process. Thepolymer layer 22, as the name suggests, is formed of a polymer, such asan epoxy, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), andthe like, although other relatively soft, often organic, dielectricmaterials can also be used. In one embodiment, the polymer layer 22 is apolyimide layer. In another embodiment, the polymer layer 22 is apolybenzoxazole (PBO) layer. The polymer layer 22 is soft, and hence hasthe function of reducing inherent stresses on respective substrate. Inaddition, the polymer layer 22 is easily formed to a thickness of tensof microns.

Referring to FIG. 2, the formation of an under-bump-metallurgy (UBM)layer 24 that includes a diffusion barrier layer and a seed layer isperformed on the resulted structure. The UBM layer 24 is formed on thepolymer layer 22 and the exposed portion of the PPI line 18, and linesthe sidewalls and bottom of the opening 23. The diffusion barrier layer,also referred to as a glue layer, is formed to cover the sidewalls andthe bottom of the opening 23. The diffusion barrier layer may be formedof tantalum nitride, although it may also be formed of other materialssuch as titanium nitride, tantalum, titanium, or the like. The formationmethods include physical vapor deposition (PVD) or sputtering. The seedlayer may be a copper seed layer formed on the diffusion barrier layer.The seed layer may be formed of copper alloys that include silver,chromium, nickel, tin, gold, and combinations thereof. In oneembodiment, the UBM layer 24 includes a diffusion barrier layer formedof Ti and a seed layer formed of Cu.

Next, a mask layer 26 is provided on the UBM layer 24 and patterned withan opening 27 exposing a portion of the UBM layer 24 for Cu pillar bumpformation. In one embodiment, the opening 27 is over the opening 23. Inanother embodiment, the diameter of the opening 27 is greater or equalto the diameter of the opening 23. The mask layer 26 may be a dry filmor a photoresist film. The opening 27 is then partially or fully filledwith a conductive material with solder wettability. In an embodiment, acopper (Cu) layer 28 is formed in the opening 27 to contact theunderlying UBM layer 24. As used throughout this disclosure, the term“copper (Cu) layer” is intended to include substantially a layerincluding pure elemental copper, copper containing unavoidableimpurities, and copper alloys containing minor amounts of elements suchas tantalum, indium, tin, zinc, manganese, chromium, titanium,germanium, strontium, platinum, magnesium, aluminum or zirconium. Theformation methods may include sputtering, printing, electro plating,electroless plating, and commonly used chemical vapor deposition (CVD)methods. For example, electro-chemical plating (ECP) is carried out toform the Cu layer 28. In an exemplary embodiment, the thickness of theCu layer 28 is greater than 30 μm. In another exemplary embodiment, thethickness of the Cu layer 28 is greater than 40 μm. For example, the Culayer 28 is of about 40-50 μm thickness, or about 40-70 μm thickness,although the thickness may be greater or smaller.

Next, as shown in FIG. 3, the mask layer 26 is removed, exposing aportion of the UBM layer 24 outside the Cu layer 28. In the case themask layer 26 is a dry film, it may be removed using an alkalinesolution. If the mask layer 26 is formed of photoresist, it may beremoved using acetone, n-methyl pyrrolidone (NMP), dimethyl sulfoxide(DMSO), aminoethoxy ethanol, and the like. Then the exposed portion ofthe UBM layer 24 is etched to expose the underlying polymer layer 22outside the Cu layer 28, thus the UBM layer 24 underlying the Cu layer28 remains. In an exemplary embodiment, the step of removing the UBMlayer 24 is a dry etching or a wet etching. For example, an isotropicwet etching (often referred to as flash etching due to its shortduration) using an ammonia-based acid is employed. Thus the Cu layer 28having a top surface 28 a and sidewall surfaces 28 b protrudes from thepolymer layer 22, also referred to as a Cu pillar bump 28 hereinafter.In an exemplary embodiment, the thickness of the Cu pillar bump 28 isgreater than 30 μm. In another exemplary embodiment, the thickness ofthe Cu pillar bump 28 is greater than 40 μm. For example, the Cu pillarbump 28 is of about 40-50 μm thickness, or about 40-70 μm thickness,although the thickness may be greater or smaller.

Next, as depicted in FIG. 4, a barrier layer 30 is formed on the Cupillar bump 28 to act as a diffusion barrier layer for preventing copperin the Cu pillar bump 28 to diffuse into bonding material, such assolder, that is used to bond the substrate 10 to external features. Thebarrier layer 30 may be also referred to as a protection layer, anantioxidation layer or an oxide resistant layer employed for preventingthe surfaces 28 a and 28 b of the Cu pillar bump 28 from oxidationduring subsequent processes. The barrier layer 30 may be formed throughdepleting surfaces of the Cu pillar bump 28 by selective thermal CVDmethod. In one embodiment, the barrier layer 32 is formed on the Cupillar 28, covering the top surface 28 a, the sidewall surfaces 28 b, orcombinations thereof. The barrier layer 30 is a copper-containingmaterial layer including a group III element, a group IV element, agroup V element listed in the periodic table or any combination thereof.In one embodiment, the copper-containing material layer may include, butis not limited to, boron (B), germanium (Ge), silicon (Si), carbon (C),nitrogen (N), phosphorous (P) or combinations thereof. In someembodiments, the copper-containing material layer is a CuGeN layer, aCuGe layer, a CuSi layer, a CuSiN layer, a CuSiGeN layer, a CuN layer, aCuP layer, a CuC layer, a CuB layer, or combinations thereof using aselective CVD with gases containing B, Ge, Si, C, N, P or combinationsthereof (e.g., B₂H₆, CH₄, SiH₄, GeH₄, NH₃, PH₃). For an example offorming a CuGeN layer, a deoxidize treatment step (NH₃ treatment) isperformed followed by a GeH₄ CVD process. The barrier layer 30 becomes adiffusion barrier layer to passivate the Cu from the solder insubsequent joint process so that the IMC formation is controlled tobecome thinner and more uniform. Besides, the thickness of the barrierlayer 30 is thin due to its formation is like a diffusion process. Inone embodiment, the thickness of the barrier layer 30 is less than orequal to 10 nm. The combination of the Cu pillar bump 28 and the barrierlayer 30 is referred to as a connection structure 32 for to bonding thesubstrate 10 to external features.

The connection structure 32 may further include a solder layer.Referring to FIG. 5, an exemplary embodiment of forming a solder layeron the Cu pillar bump is depicted. After the formation of the barrierlayer 30, a solder layer 34 may be provided on the barrier layer 30, ina position adjacent to the top surface 28 a of the Cu pillar bump 28adjacent to the sidewall surfaces of the Cu pillar bump 28 as depictedby a dotted line, or combination thereof. The solder layer 34 may bemade of Sn, SnAg, Sn—Pb, SnAgCu (with Cu weight percentage less than0.3%), SnAgZn, SnZn, SnBi—In, Sn—In, Sn—Au, SnPb, SnCu, SnZnIn, orSnAgSb, etc. The combination of the Cu pillar bump 28, the barrier layer30 and the solder layer 34 is referred to as another connectionstructure 32″ for to bonding the substrate 10 to external features.

The substrate 10 is then sawed and packaged onto a package substrate, oranother die, with solder balls or Cu bumps mounted on a pad on thepackage substrate or the other die. FIG. 6 is a cross-sectional diagramdepicting an exemplary embodiment of a flip-chip assembly.

The structure shown in FIG. 4 or FIG. 5 is flipped upside down andattached to another substrate 100 at the bottom. The substrate 100 maybe a package substrate, board (e.g., a printed circuit board (PCB)), orother suitable substrate. The connection structure 32 or 32″ contactsthe substrate 100 at various conductive attachment points, for example,a joint solder layer 104 on contact pads 102 and/or conductive traces,forming a joint structure 106 between the substrates 10 and 100. Anexemplary coupling process includes a flux application, chip placement,reflowing of melting solder joints, and cleaning of flux residue. Thesubstrate 10, the joint structure 106, and the other substrate 100 maybe referred to as a packaging assembly, or in the present embodiment, aflip-chip packaging assembly. During thermal cycling, the tin in thesolder (joint solder layer 104 and/or solder layer 34) tends to migratethrough cracks or other defects and react with the barrier layer 30and/or the Cu pillar bump 28 to form an intermetallic compound (IMC)layer 108 which may be observed between the solder joint 104 and theconnection structure 32 or 32″. The IMC layer 108 may include Cu, Sn andthe material including a group III element, a group IV element, a groupV element listed in the periodic table or any combination thereof. Forexample, The IMC layer may include a Cu—Sn—X IMC, wherein the X elementmay include, but is not limited to, boron (B), germanium (Ge), silicon(Si), carbon (C), nitrogen (N), phosphorous (P) or combinations thereof.The IMC thickness can be controlled to less than 2 μm with the diffusionbarrier layer 30. The barrier layer 30 depresses Cu diffusion from theCu pillar BUMP 28 to the solder to control the IMC layer 108 to athickness less than 2 μm, resulting in high strength and betteradhesion. The thin IMC formation can induce less stress to decreaseprobability of bump cracking and contribute to better reliability of Cupillar bump.

FIG. 7 is a cross-sectional diagram depicting an exemplary embodiment ofa flip-chip assembly. Depending on the solder volume and substrateattaching processes, the joint solder layer 104 may cover at least aportion of the connection structure 32 or 32″, for example the topportion and/or sidewall portions. When the joint solder layer 104 coversthe sidewall portions of the connection structure 32 or 32″ as depicted,the IMC layer 108 is also observed between the sidewall portion of theconnection structure 32 or 32″ and the joint solder layer 04.

In the preceding detailed description, the disclosure is described withreference to specific exemplary embodiments thereof. It will, however,be evident that various modifications, structures, processes, andchanges may be made thereto without departing from the broader spiritand scope of the disclosure. The specification and drawings are,accordingly, to be regarded as illustrative and not restrictive. It isunderstood that the disclosure is capable of using various othercombinations and environments and is capable of changes or modificationswithin the scope of inventive concepts as expressed herein.

1. An integrated circuit device, comprising: a semiconductor substrate;a bond pad region on the semiconductor substrate; a copper pillar bumpoverlying and electrically connected to the bond pad region; and abarrier layer on a surface of the copper pillar bump, wherein thebarrier layer is a copper-containing material layer comprising at leastone of a group III element, a group IV element and a group V element. 2.The integrated circuit device of claim 1, wherein the barrier layer is aCuGeN layer.
 3. The integrated circuit device of claim 1, wherein thebarrier layer is a copper-containing material layer comprising at leastone of germanium (Ge), silicon (Si) and carbon (C).
 4. The integratedcircuit device of claim 1, wherein the barrier layer is acopper-containing material layer comprising at least one of nitrogen (N)or phosphorus (P).
 5. The integrated circuit device of claim 1, whereinthe barrier layer is a copper-containing material layer comprising boron(B).
 6. The integrated circuit device of claim 1, further comprising asolder layer on the barrier layer.
 7. The integrated circuit device ofclaim 1, further comprising: a passivation layer overlying thesemiconductor substrate and exposing a portion of the bond pad region;an interconnect line formed on the passivation layer and electricallyconnected to the bond pad region; and a polymer layer overlying thepassivation layer and exposing a portion of the interconnect line;wherein the copper pillar bump is formed overlying the polymer layer andelectrically connected to the exposed portion of the interconnect line.8. The integrated circuit device of claim 7, wherein the interconnectline comprises copper.
 9. The integrated circuit device of claim 7,wherein the passivation layer comprises polybenzoxazole (PBO).
 10. Theintegrated circuit device of claim 7, wherein the polymer layercomprises polybenzoxazole (PBO).
 11. A flip-chip assembly comprising: afirst substrate; a second substrate; a joint structure disposed betweenthe first substrate and the second substrate; wherein the jointstructure comprises a connection structure between the first substrateand the second substrate and a joint solder layer between the connectionstructure and the second substrate; and an intermetallic compound (IMC)layer between the connection structure and the joint solder layer,wherein the IMC layer has a thickness less than 2 μm.
 12. The flip-chipassembly of claim 11, wherein the connection structure comprises acopper pillar bump.
 13. The flip-chip assembly of claim 12, wherein theconnection structure comprises a barrier layer on a surface of thecopper pillar bump.
 14. The flip-chip assembly of claim 13, wherein thebarrier layer is a copper-containing material layer comprising at leastone of a group III element, a group IV element and a group V element.15. The flip-chip assembly of claim 13, wherein the barrier layer is aCuGeN layer.
 16. The flip-chip assembly of claim 13, wherein thecopper-containing material layer comprises at least one of germanium(Ge), silicon (Si) or carbon (C).
 17. The flip-chip assembly of claim13, wherein the copper-containing material layer comprises at least oneof nitrogen (N) or phosphorus (P).
 18. The flip-chip assembly of claim13, wherein the copper-containing material layer comprises boron (B).19. The flip-chip assembly of claim 11, wherein the first substratecomprises: a passivation layer overlying the first substrate; aninterconnect line formed on the passivation layer; and a polymer layeroverlying the passivation layer and exposing a portion of theinterconnect line; wherein the connection structure is overlying andelectrically connected to the exposed portion of the interconnect line.20. The flip-chip assembly of claim 19, wherein the interconnect linecomprises copper, and the polymer layer comprises polybenzoxazole (PBO).